Hardware Verification Engineer - Edison Smart

The role focuses on defining and executing verification strategies to ensure high-quality, high-performance hardware IP, working closely with design and architecture teams. Key Responsibilities Develop and execute RTL verification environments, test plans, and coverage Build and maintain verification testbenches in SystemVerilog, C++, and Python Create and manage BFMs, monitors, and checkers Improve verification flows, automation, and coverage metrics Collaborate with RTL and architecture teams to resolve issues Key Requirements 4+ years’ experience in hardware verification Strong RTL knowledge and experience with UVM and EDA tools Proficiency in SystemVerilog, C++, Python (VHDL/SystemC a plus) Experience with on-chip communication protocols (e.g.