May be filled
Lead Design Verification Engineer
Redmond, Washington, Vereinigte Staaten von Amerika
2026-01-31
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Powered by ClaudeJob title: Lead Design Verification Engineer Location: Redmond / Seattle, WA He should have some lead experience, even hands on experience in also fine. Job Description: Design Verification expertise in System Verilog /UVM for Unit/Module level Verification Should have Lead Design Verification Team (Min 5 Members) Strong background in developing UVM Testbenches from scratch Experience in VIP Integration and Bring up Porting Existing Verilog/VHDL environment to UVM based Environment Experience i…
Job description
Job title: Lead Design Verification Engineer Location: Redmond / Seattle, WA He should have some lead experience, even hands on experience in also fine. Job Description: Design Verification expertise in System Verilog /UVM for Unit/Module level Verification Should have Lead Design Verification Team (Min 5 Members) Strong background in developing UVM Testbenches from scratch Experience in VIP Integration and Bring up Porting Existing Verilog/VHDL environment to UVM based Environment Experience in test planning, Coverage Coding and Debugging Deep Knowledge of AMBA Protocol is must Show less
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